Simulation of video processing on an RISC-V processor with a gem5 simulator

Simulacijom procesora i računalnih sustava omogućava se istraživanje u području arhitekture i organizacije računala. Dostupno je nekoliko takvih platformi koje omogućuju simulaciju, emulaciju i sintezu proizvoljnih arhitektura skupa instrukcija. Predstavlja se građa gem5 simulatora, opisuju specifičnosti RISC-V skupa instrukcija te implementacija RISC-V ISA u gem5 simulatoru. Postavlja se testni sustav, popravljaju neki problemi implementacije i analiza trenutni problem simulacije cijelog sustava s RISC-V procesorom na gem5 platformi.Simulation of processors and computer systems enables research in the field of computer architecture and organisation. Several such platforms are available that allow the simulation, emulation, and synthesis of arbitrary instruction set architectures. The structure of the gem5 simulator is presented, the specifics of the RISC-V instruction set and the implementation of the RISC-V ISA in the gem5 simulator are described. A test system is set up, some implementation problems are fixed and the current problem of simulating the whole system with a RISC-V processor on a gem5 platform is analyse