An efficient packet parser architecture for software-defined 5G networks

Software-defined networks (SDN) has emerged with the capability to program in order to enhance flexibility, management, and testing of new ideas in the next generation of networks by removing current network limitations. Network virtualization and functionalization are critical elements supporting the delivery of future network services, especially in 5G networks. With the integration of virtualization and functionalization, network resources can be provisioned on-demand, and network service functions can be composed and chained dynamically to cater to various requirements. 5G networks are expected to rely heavily on SDN, which has been widely applied in core network design. To have a software-defined 5G network, not only is new spectrum and interface needed from SDN, but also a programmable and efficient hardware infrastructure is required. Admittedly, hardware components and infrastructure play an important role in supporting 5G networks. In other words, the software-defined 5G network data plane must have the required flexibility and programmability to support upcoming needs and technologies. Technological solutions need to respond to actual requests in infrastructure. Packet parsers in the data plane of software-defined 5G networks are one of the most important components because of the variation in the type of network headers and protocols. Each SDN switch needs to identify headers for processing input packets in the data plane, where the packet parser operates. Multiple implementations of packet parsers have been done on different substrates that occupy large hardware resources and areas on chip. However, they are not suitable for software-defined 5G networks. Certain architectures have been presented for packet parsing, aimed at accelerating the process of header parsing, however no attention has been paid toward reducing the area and the volume of the needed hardware resources and programmability in the data plane. This paper presents a new and efficient architecture for packet parsers on Field Programmable Gate Arrays (FPGA), called Efficient FPGA Packet Parser (EFPP) in a designed software-defined 5G network. This architecture emphasizes the removal of Ternary Content Addressable Memory (TCAM) to decrease hardware resources and efficiency in the data plane. Moreover, this architecture uses the chip\u27s processing speed and reconfiguration capabilities to support new protocols and network headers while maintaining flexibilities on software-defined 5G networks. EFPP is applied to chips on FPGA Xilinx ZedBoard Zynq, and the resources consumed around 7.5% LookUp Table, 1.9% Flip-Flops, and 5.8% of the memory. EFPP was also more area efficient. According to our results, EFPP would reduce the area and volume of hardware compared to other peer works