TEST: Assessing NoC policies facing aging and leakage power

The trend to increase the number of cores integrated on a single die makes Networks-on-Chip (NoCs) a key component from the interconnection viewpoint. Unfortunately, continuous scaling of CMOS technology poses severe concerns regarding failure mechanisms, such as NBTI, that are crucial in achieving a reasonable component lifetime. Furthermore, the leakage power became more and more a critical issues as the technology scales up. Finally, Process Variation (PV) makes harder the scenario, decreasing device lifetime and performance predictability during chip fabrication. Several techniques have been presented in literature facing the NBTI and or the static power consumption. This paper proposes a methodology to analyze such techniques from the feasibility viewpoint. It is explored their effectiveness in contrasting NBTI and saving static power in the NoC as well as the associated overheads and drawbacks. For the two considered policies, it is achieved a NBTI mitigation up to 55% and a power saving up to 51% with performance and area overheads less than 10% and 5%, respectively