TDC with 1.5% DNL based on a single-stage vernier delay-loop fine interpolation

We present a compact TDC Module based on the Time-to-Digital Converter ASIC fabricated in 0.35 μm CMOS technology. This chip measures the time-interval between two inputs, called START and STOP, with a 10 ps resolution when using a 10 ns reference clock. Thanks to the structure, composed by two independent “interpolators” for each input and a “coarse” counter, the TDC chip can reach an average precision better than 15 psRMS and a differential non-linearity (DNL) smaller than 0.9 %LSB with a maximum conversion rate of about 3 Msps. A simple calibration allows to compute proper coefficients to apply to raw data. The TDC Module is composed by two SMA inputs, followed by an electronic front-end to provide compatibility to any kind of signal, an USB 2.0 connector for parameters setting and data upload to a remote computer and the power supply connector