Two-Dimensional Sequential Array Architectures: Design for Testability Approaches

Testing of array architectures is an important issue because of the relevance that these structures are assuming in VLSI/WSI designs. The DfT techniques presented in this paper represent a possible approach to allow the verification of the cells composing the entire structure. The structural methodologies cope with the accessibility problems by modifying the interconnection network to “isolate” the cell in exam from the others; the functional approach modifies the cell making it transparent with respect to the data flow if the cell is not being tested. Both techniques aim at defining a sequential array architecture whose elements can be tested by applying patterns defined for the single cell and achieving the same coverage notwithstanding the embedding constituted by the array interconnections