Add to ORKGAim of this paper is to present a self-testable FIFO memory macrocell, which can be embedded into larger devices. A dual port RAM-type FIFO has been designed. A new test procedure for the macrocell has been defined aiming at detecting all possible faults in the control logic and the RAM cell. Given such a rest procedure the appropriate Built-In Self rest architecture has been defined, independently of the memory size. Fault coverage and area overhead for the proposed solution are presented
Abstract- Embedded RAMs are those whose address, data, and read/write controls cannot be directly co...
A new approach to diagnostic testing of embedded memories is presented which enables the design of t...
ISBN 0-7803-9038-5International audienceIn modern SoCs embedded memories include the large majority ...
Aim of this paper is to present a self-testable FIFO memory macrocell, which can be embedded into la...
Embedded first-in first-out (FIFO) memories are increasingly used in many IC designs. We have create...
Test algorithms and determining factors in choosing a repair architecture -- Global architecture and...
[[abstract]]In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM core...
ABSTRACT: We present a Built-In Self-Test (BIST) ap-proach for programmable embedded memories in Xil...
The design and architecture of a reconfigurable memory BIST unit is presented. The proposed memory B...
[[abstract]]Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC...
Abstract—As there are increasing functionalities in modern system-on-chip (SOC) design, the amount o...
A self-testing circuit design methodology is developed for off-line testing of regular or nearly reg...
[[abstract]]The objective of this paper is to present a cost-effective fault diagnosis methodology f...
Embedded First-In First-Out (FIFO) memories are increasingly used in many IC designs. We have create...
ISBN: 0818621575The authors present a novel approach to the test of multi-port RAMs. A novel fault m...
Abstract- Embedded RAMs are those whose address, data, and read/write controls cannot be directly co...
A new approach to diagnostic testing of embedded memories is presented which enables the design of t...
ISBN 0-7803-9038-5International audienceIn modern SoCs embedded memories include the large majority ...
Aim of this paper is to present a self-testable FIFO memory macrocell, which can be embedded into la...
Embedded first-in first-out (FIFO) memories are increasingly used in many IC designs. We have create...
Test algorithms and determining factors in choosing a repair architecture -- Global architecture and...
[[abstract]]In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM core...
ABSTRACT: We present a Built-In Self-Test (BIST) ap-proach for programmable embedded memories in Xil...
The design and architecture of a reconfigurable memory BIST unit is presented. The proposed memory B...
[[abstract]]Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC...
Abstract—As there are increasing functionalities in modern system-on-chip (SOC) design, the amount o...
A self-testing circuit design methodology is developed for off-line testing of regular or nearly reg...
[[abstract]]The objective of this paper is to present a cost-effective fault diagnosis methodology f...
Embedded First-In First-Out (FIFO) memories are increasingly used in many IC designs. We have create...
ISBN: 0818621575The authors present a novel approach to the test of multi-port RAMs. A novel fault m...
Abstract- Embedded RAMs are those whose address, data, and read/write controls cannot be directly co...
A new approach to diagnostic testing of embedded memories is presented which enables the design of t...
ISBN 0-7803-9038-5International audienceIn modern SoCs embedded memories include the large majority ...
