A new methodology for defining self-checking sequential architectures is presented in the paper. A m-out-of-n encoding of the juxtaposition of next-state and output eventually completed with additional output lines, is provided. The goal is guaranteeing detection of single and multiple unidirectional errors while minimizing area overhead
ABSTRACT A number of methods have been published to construct checking sequences for testing from Fi...
A new architecture for matching the data protected with an error-correcting code (ECC) is presented ...
Encoding techniques and dedicated self-checking architectures cart be conveniently adopted in VLSI d...
A new methodology for defining self-checking sequential architectures is presented in the paper. A m...
The design of self-checking FSMs can be achieved by adopting an encoding for the state, for the outp...
The design of self-checking systems is a viable approach for coping with critical applications, guar...
A method of a self-checking synchronous Finite State Machine (FSM) network design with low overhead ...
Abstract—In digital sequential systems that operate over several time steps, a state-transition faul...
This paper presents a complete methodology to design a totally self-checking (TSC) sequential system...
A new method for constructing a checking sequence for finite state machine based testing is introduc...
Due to reduction in device feature size and supply voltages the probability of soft-errors in Finite...
Part 1: Model Based TestingInternational audienceA new method for constructing a checking sequence f...
State space exploration of finite state machines is used to prove properties about sequential behavi...
The paper introduces a new approach for designing of self-checking Microprogram Control Units (MCU)....
ABSTRACT A number of methods have been published to construct checking sequences for testing from Fi...
A new architecture for matching the data protected with an error-correcting code (ECC) is presented ...
Encoding techniques and dedicated self-checking architectures cart be conveniently adopted in VLSI d...
A new methodology for defining self-checking sequential architectures is presented in the paper. A m...
The design of self-checking FSMs can be achieved by adopting an encoding for the state, for the outp...
The design of self-checking systems is a viable approach for coping with critical applications, guar...
A method of a self-checking synchronous Finite State Machine (FSM) network design with low overhead ...
Abstract—In digital sequential systems that operate over several time steps, a state-transition faul...
This paper presents a complete methodology to design a totally self-checking (TSC) sequential system...
A new method for constructing a checking sequence for finite state machine based testing is introduc...
Due to reduction in device feature size and supply voltages the probability of soft-errors in Finite...
Part 1: Model Based TestingInternational audienceA new method for constructing a checking sequence f...
State space exploration of finite state machines is used to prove properties about sequential behavi...
The paper introduces a new approach for designing of self-checking Microprogram Control Units (MCU)....
ABSTRACT A number of methods have been published to construct checking sequences for testing from Fi...
A new architecture for matching the data protected with an error-correcting code (ECC) is presented ...
Encoding techniques and dedicated self-checking architectures cart be conveniently adopted in VLSI d...
DOI
Add to ORKG