A design methodology for the correct specification of VLSI systems

Time to market is a key factor to beat competitors as it measures the ability to satisfy the market demands at the proper time. Innovative design methodologies based on formal methods can positively affect this parameter allowing rigour of design practice and guaranteeing correctness of implementations. In this paper we introduce the methodological approach based on the use of the specification language VHDL/S and of the related formal based tools. The final goal is to provide an environment able to support the designer in the specification phase with the generation of correct and verified VHDL code. The integration of this formal based design phase into a standard CAD design flow is managed through the restriction to the VHDL subset supporting logical synthesis. Finally the encapsulation into a commercial CAD framework guarantees the unified approach to design required by final users