A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells

Nowadays, design issues related to physical design and scalability are becoming the main bottlenecks of modern tools for technology mapping, limiting the usage of large cells. On the other hand, the generation of regular macro cells, such as compound gates, are becoming interesting from the manufacturing point of view, but they need to be properly integrated into the existing industrial design flows. In this paper, we present an efficient methodology for identifying the cells that can extend an existing standard-cell library. We validated our approach on different benchmarks targeting area minimization and we also analyzed timing, power consumption and routing effects for the final circuit implementation