Address Bus Encoding Techniques for System-Level Power Optimization

The Design Automation and Test in Europe, DATE, is Europe’s leading international electronic systems design conference for electronic design, automation and test, from system level hardware and software implementation right down to integrated circuit design. It combines the conference with Europe’s leading international exhibition for electronic design, automation and test. To celebrate the tenth anniversary of DATE, the Editors have compiled this book with the aim to highlight some of the most influential technical contributions from ten years of DATE. Selecting 30 papers, only 3 papers from each year, is a challenging endeavor. Although the impact of papers from the first years of DATE can be determined through various citation indexes, the impact from the later years still have to be seen. Together with all 10 Program Chairs, the Editors have made a selection of the most influential papers covering the very broad range of topics which is characteristic for DATE. The present chapter discusses how the power dissipated by system-level buses is the largest contributionbto the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I/O interfaces can provide significant savings on the overallbpower budget. This paper presents innovative encoding techniques suitable for minimizing the switching activity of system-level address buses. In particular, the schemes illustrated here target the reduction of the average number of bus line transitions per clock cycle. Experimental results, conducted on address streams generated by a real microprocessor, have demonstrated the effectiveness of the proposed methods