This paper presents an analysis of the influence of parasitic inter-electrode capacitances of the components of logarithmic analogue-to-digital converters with successive approximation with a variable logarithm base. Mathematical models of converter errors were developed and analyzed taking into account the parameters of modern components. It has been shown that to achieve satisfactory accuracy for the 16 bit LADC, the capacitance of the capacitor cell must not be less than 10 nF; for the 12 bit LADC, 1 nF is sufficient
This paper analyses the performance of a recently proposed background calibration technique with dig...
textIt is very challenging to build precise analog circuits in deep sub-micron and nanometer VLSI f...
A low-power 14-bits first order incremental Analog-to-Digital Converter (ADC) is presented. Based on...
W artykule przedstawiono analizę logarytmicznego analogowo-cyfrowego przetwornika (LPAC) z sukcesywn...
Indexing terms concert or^, Circuit theory and desiyn Abstract: The paper presents two switched-capa...
This article is a presentation of the analysis of new class of logarithmic analog-to-digital convert...
This article is a presentation of the analysis of new class of logarithmic analog-to-digital convert...
textAnalog-to-digital converters (ADCs) are driven by rapid development of mobile communication syst...
Abstract: The advantages of a signal processing in the logarithmic domain are recently pointed out b...
International audienceThis paper analyses a BiCMOS integrated circuit for interfacing capacitive sen...
We measure the coefficients of self capacitance C11and of interelectrode capacitance C12of a pair of...
This paper presents a multi-input analogue-to-digital functional converter manufactured using switch...
Pipeline analog-to-digital converters (ADC) are widely used to achieve high resolution and moderatel...
Abstract:- This paper describes some error cancellation approaches used in ADC exploiting switched c...
In the last few years several new digital methods have been developed for capacitance ...
This paper analyses the performance of a recently proposed background calibration technique with dig...
textIt is very challenging to build precise analog circuits in deep sub-micron and nanometer VLSI f...
A low-power 14-bits first order incremental Analog-to-Digital Converter (ADC) is presented. Based on...
W artykule przedstawiono analizę logarytmicznego analogowo-cyfrowego przetwornika (LPAC) z sukcesywn...
Indexing terms concert or^, Circuit theory and desiyn Abstract: The paper presents two switched-capa...
This article is a presentation of the analysis of new class of logarithmic analog-to-digital convert...
This article is a presentation of the analysis of new class of logarithmic analog-to-digital convert...
textAnalog-to-digital converters (ADCs) are driven by rapid development of mobile communication syst...
Abstract: The advantages of a signal processing in the logarithmic domain are recently pointed out b...
International audienceThis paper analyses a BiCMOS integrated circuit for interfacing capacitive sen...
We measure the coefficients of self capacitance C11and of interelectrode capacitance C12of a pair of...
This paper presents a multi-input analogue-to-digital functional converter manufactured using switch...
Pipeline analog-to-digital converters (ADC) are widely used to achieve high resolution and moderatel...
Abstract:- This paper describes some error cancellation approaches used in ADC exploiting switched c...
In the last few years several new digital methods have been developed for capacitance ...
This paper analyses the performance of a recently proposed background calibration technique with dig...
textIt is very challenging to build precise analog circuits in deep sub-micron and nanometer VLSI f...
A low-power 14-bits first order incremental Analog-to-Digital Converter (ADC) is presented. Based on...