Dynamic Reconfiguration: Core Relocation via Partial Bitstreams Filtering with Minimal Overhead

Partial reconfiguration is a relatively new feature of FPGAs and it allows the modification of hardware functionalities at runtime, providing the possibility for great improvements in the concept of reconfigurable computing. However, this new approach also creates some problems in the implementation phase of modules and in their placement. By restricting the form of single functions to arrays of whole columns communicating on a single horizontal bus, the problem can be significantly simplified. Column-wise partial reconfiguration can be realized by means of a space allocation manager that determines the columns where single modules should be placed and a component which modifies the bitstream to place it in the correct position. This paper describes the development of such component in the form of the bitstream relocation filter, BiRF, that allows the relocation of a partial bitstream with minimal overhead during the download process. The proposed solution is thought starting from the REPLICA filter, trying to adapt it to work within the fixed side of the Caronte architectur