An Area Estimation Methodology for FPGA Based Designs at SystemC-Level

This paper presents a parametric area estimation methodology 'at SystemC level for FPGA-based designs. The ap proach is conceived to reduce the effort to adapt the area e6 timators to the evolutions of the EDA design environments. It coisists in identifying the subset of measures that can be derived form the system level description and that are also relevant at VHDL-RT level. Estimators' parameters are then automatically derived from a set of benchmarks