Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures

This paper presents a methodology and framework to model the behavior of superscalar microprocessors. The simulation is focused on timing analysis and ignores all functional aspects. The methodology also provides a framework for building new simulators for generic architectures. The results obtained show a good accuracy and a satisfactory computational efficiency. Furthermore, the C++ SDK allows rapid development of new processor models making the methodology suitable for design space exploration over new processor architectures