This paper proposes a system-level design methodology for the efficient exploration of the memory architecture from the energy-delay combined perspective. The aim is to find a sub-optimal configuration of the memory hierarchy without performing the exhaustive analysis of the parameters spac
This paper presents a novel delay model for MCML circuits valid in all the regions of operation of t...
This paper describes the architectural exploration of the system-level parameters for a MicroSPARC2-...
152 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2009.We propose a methodology for ...
This paper proposes a system-level design methodology for the efficient exploration of the memory ar...
Comprehensive exploration of the design space parameters at the system-level is a crucial task to ev...
In this paper, we propose a system-level design methodology for the efficient exploration of the arc...
In this paper we introduce an energy-delay efficiency metric that captures any trade-off between the...
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
Abstract—This paper represents a departure from the conventional methods of design and analysis of c...
This paper relates the potential energy savings to the energy profile of a circuit. These savings ar...
In this paper, the energy-delay tradeoff that can be realized between energy and delay for MCML gate...
Thesis (Ph. D.)--University of Rochester. Department of Electrical and Computer Engineering, 2016.Si...
In embedded system design, the designer has to choose an onchip memory configuration that is suitabl...
In this paper, general metrics of the energy-delay (E-D) tradeoff in digital VLSI circuits are discu...
In designing a new processor, computer architects consider a myriad of possible organizations and de...
This paper presents a novel delay model for MCML circuits valid in all the regions of operation of t...
This paper describes the architectural exploration of the system-level parameters for a MicroSPARC2-...
152 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2009.We propose a methodology for ...
This paper proposes a system-level design methodology for the efficient exploration of the memory ar...
Comprehensive exploration of the design space parameters at the system-level is a crucial task to ev...
In this paper, we propose a system-level design methodology for the efficient exploration of the arc...
In this paper we introduce an energy-delay efficiency metric that captures any trade-off between the...
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
Abstract—This paper represents a departure from the conventional methods of design and analysis of c...
This paper relates the potential energy savings to the energy profile of a circuit. These savings ar...
In this paper, the energy-delay tradeoff that can be realized between energy and delay for MCML gate...
Thesis (Ph. D.)--University of Rochester. Department of Electrical and Computer Engineering, 2016.Si...
In embedded system design, the designer has to choose an onchip memory configuration that is suitabl...
In this paper, general metrics of the energy-delay (E-D) tradeoff in digital VLSI circuits are discu...
In designing a new processor, computer architects consider a myriad of possible organizations and de...
This paper presents a novel delay model for MCML circuits valid in all the regions of operation of t...
This paper describes the architectural exploration of the system-level parameters for a MicroSPARC2-...
152 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2009.We propose a methodology for ...