Configurable network-on-chip router macrocells

This paper presents a configurable architecture for Network-on-Chip (NoC) router macrocells, and a methodology to streamline their design and configuration. The methodology addresses the typical problems experienced by design and verification engineers when coding highly configurable intellectual property macrocells at Register Transfer Level (RTL) with hundreds of parameters and thousands of resulting configurations. A NoC infrastructure for a Multi Processor System-on-Chip (MPSoC) may require tens or hundreds of router macrocells. Therefore, managing the configuration design space is becoming a bottleneck for the design and verification of many-core processing systems. The proposed generation flow is illustrated on a real-world NoC router core. Its configurable architecture is compliant with several NoC topologies such as Ring, Octagon, Spidergon and 2D mesh typically used in many-core processing platforms. The generation flow allows for a reduction in the database code size, up to 70% in our experiments, and a contraction of three orders of magnitudes of the verification space vs. conventional design flows of RTL macrocells. The validity of the approach is also confirmed by synthesizing the generated router macrocells in nanoscale CMOS technology. The achieved performance compare well to the state-of-the-art in terms of low latency and low circuit complexit