Low power open-loop ICO-based sigma-delta ADCs for sensor systems

Precision sensor systems require low-noise analog front-end and low-power analog-to-digital converters (ADCs) for processing. To lower power, scaled CMOS technologies use reduced supply voltages which limit the headroom and Signal-to-Noise ratio (SNR), but avails high-resolution clock and time-based circuits to represent analog signals, which makes analog to digital conversion in time-domain more convenient than voltage-domain. This thesis presents a new continuous-time open-loop time-domain Sigma Delta (S-D) ADC architecture with a current input and a capacitor to integrate it linearly. Due to the shortage of headroom in scaled CMOS, the integral is folded at two precisely controlled voltage levels in opposite direction forming a triangular waveform. This offers linear integration with the integral represented partially in digital (Digital Output) and partially in analog (Quantization error) allowing several energy-efficient techniques to finer approximate the error, enhancing the resolution of the ADC including, • Finerflash: Adding and detecting finer voltage levels within the triangle (multi-bit quantization) at the sampling instant. Prototype ICs fabricated in TSMC 180nm CMOS achieved FoM [subscript W] of 1104 fJ/step and FoM [subscript S,DR] of 161 dB. • Subranging: Running the ICO at nominally lower frequency for most of the sampling period and increasing its frequency close to the sampling instant allows to simultaneously achieve high resolution and low power consumption. Prototype ICs fabricated in TSMC 180nm CMOS achieved FoM [subscript W] of 675 fJ/step and FoM [subscript S,DR] of 166 dB. The performance of the prototype ICs is comparable to the state-of-the-art ADCs for low-bandwidth applications in terms of power and figure-of-merit. In addition, the simplicity of implementation of this new architecture opens up a new design arena for high-performance ADCs in shorter channel technologies. The latter part of this thesis presents the demonstration of low-noise analog front-end circuits using a novel symmetric dual-gate MoS₂ transistor. A study on the effect of symmetry of the two gates on the I-V characteristics is made. A chopper amplifier with a single MoS₂ transistor is realized using a single transistor to frequency translate the low-bandwidth input signal to get the signal away from the noise corner with a nominal gain factor.Electrical and Computer Engineerin