Highly Efficient Wideband Digital Frequency Demultiplexer

This paper presents an advanced ASIC architecture for a wideband digital frequency demultiplexer designed for on board satellite communication systems. The structure is able to handle up to 32 uniformly spaced channels extracted from a digital, real frequency division multiplexed signal sampled at 672 MHz; contiguous demultiplexing and remultiplexing is supported. An efficient demux two-stage parallel architecture was developed where all internal coefficients (including the FFT ones) are coded with canonic signed digit technique allowing area saving with respect to 2's complement code. Performance evaluations, in terms of bit error rate, noise to power ratio and gate complexity, were carried out for the architecture definition. Subsequently the design was coded in VHDL and synthesised on a 0.18 μm CMOS technology by means of Synopsys™ tools