Application specific behavioral syntehsis design space exploration: artifical neural networks

C-based VLSI design some distinct advantages over traditional RT-Level VLSI design. One key advantage is the ability to automatically generate different types of microarchitectures from the original behavioral description. This allows to explore the design space obtaining micro-architectures with unique characteristics. The main problem with previous work on High-Level Synthesis (HLS) Design Space Exploration (DSE) is that the given behavioral description is assumed to be stable and thus, that it has been fully refined a priori. For many application e.g. Artificial Neural Networks (ANNs) it is not easy to refine the input description as numerous parameters like the number of neurons and layers combined with the duration of the training phase is nontrivial and any changes in these parameters significantly affects the resultant hardware circuit. Thus, this work proposes a tightly integrated two-tier application specific HLS DSE method which explores input parameters of the behavioral description and performs a detailed HLS exploration for the best configurations which meet a set of specified input constraints and then maps the optimal design to a configurable SoC FPGA. A case study using different types of ANNs is presented. The design flow has been fully automated and the experimental results show that our proposed flow is extremely effective