Digitally Intensive RF/Millimetre-Wave Frequency Generation Techniques

The advanced wireless communication standards (e.g., 5G) placed stringent specifications on the RF/mm-wave transceivers. As a main contributor to the total error vector magnitude (EVM), the local oscillator (LO) has been attracting many research interests. This thesis presents a number of techniques to address several major challenges in designing a digitally-intensive phase-locked loop (PLL) as an LO generator in RF/mm-wave transceivers. The first half of the thesis focuses on the design of the digitally controlled oscillator (DCO), which is the most important building block in a high-performance digitally-intensive PLL. More specifically, the issue of 1/$f^3$ phase noise (PN) in a DCO attracts extensive attention along the way to pursue ultralow phase noise (PN) DCO. Moreover, this problem is getting even worse with the CMOS transistors being scaled down and thereby causing serious flicker noise in the devices. To tackle this problem, we introduce a phase shift between the gate and drain nodes of the cross-coupled pair in a transformer-based resonance tank, to mitigate the detrimental effects of ill-behaved harmonics. The phase-shifting technique has been implemented and verified with a number of measured silicon chips across frequency bands. Another contribution is a method to resolve the rarely discussed $\pm90\degree$ mode ambiguity in mm-wave quadrature oscillators. Implemented by the transformer, the phase shift inserted in the quadrature coupling path makes the oscillator favor one mode over another. A phasor-based explanation is also included for a better intuitive understanding. In doing this, we constructed a theoretical framework based on phase shift to simultaneously reduce $1/f^3$ PN and resolve the mode ambiguity. The emphasis of the second half of the thesis is on the design of several other key building blocks in the PLL. Recently, fractional-$N$ operation based on the digital-to-time converter (DTC) is becoming increasingly popular, as it helps to push the border of the PLL figure-of-merit (FoM). Since the performance of low-jitter PLLs is usually limited by the in-band PN, the design of the reference path should be carefully considered. There are several blocks in the reference path, i.e., the crystal oscillator (XO), the low-noise clock buffer, and the DTC. Unfortunately, the power consumed by these building blocks is often forgotten and omitted in the total power calculation of the PLL. To improve energy efficiency, we propose a low noise reference path suitable for fractional-$N$ operation. With an integrated XO, the DTC takes advantage of the sinusoidal waveform and operates in the voltage domain. By eliminating the front-end buffer and optimizing the XO and the DTC together, a low-jitter, low-power clock with programmable delay can be obtained. Furthermore, to bring the mm-wave output frequency to a frequency close to the reference clock, a frequency divider chain is an integral element in high-frequency PLLs which typically burn a considerable power. In this thesis, we have verified a wide locking range (LR) in a low-power, high-division ratio ring-based injection-locked frequency divider (ILFD) with the support of an analysis based on impulse-sensitivity function (ISF)