A Stochastic Model of Multiprocessor Access to an Interleaved Memory ; CU-CS-006-72

In this paper we creat a model of the way in which preocessors access a shared central memory. We investigate the way in which overall system efficiency increases as the amount of central memory interleaving is increased. We discover that studies such as this can have profound importance. For example, we see that a two-processor computer system having the characteristics of our model will lose about 70% of the processing power of one of its processors if central memory is only two-way interleaved. This loss of power drops sharply for four-, eight- and sixteen-way interleaving. At the end of the paper we also advance proposals for sharpening this admittedly-crude model and for modeling n-processor systems