VLIW architecture compilation-simulation and its implementation into FPGA

International audienceEmbedded systems present a tremendous opportunity to customize designs by exploiting the application behavior. Shrinking time-to-market, coupled with short product lifetimes, create a critical need for rapid exploration and evaluation of candidate architectures achievement of these constraint. In the recent years, these systems have grown to the new concepts with inner computing processing for improving the performance that will be known as embedded computing system. Embedded computing with VLIW (Very Long Instruction Word) based architecture has been alternative choice to implement the target application into electronics devices in many areas such as digital image processing, telecommunication, and automobile devices. Working in this architecture needs compiler which has heavy tasks especially to implement scheduling algorithm for multi-operation instructions. VLIW compiler with retargetable architecture and Instruction Level Parallelism (ILP) ability could be improvement systems performance for reducing its embedded computing design constraints. Some VLIW architecture exploitation tools have been investigated to obtain the good model before its implementation into FPGA devices, there are VEX C compiler, Code Composer Studio, and OpenIMPACT compiler. In this paper, we propose a new methodology to enable retargetable VLIW processor into FPGA. It is based on the OpenIMPACT compiler model that provides an Intermediate Representation knows as Lcode with superblock formation optimization. This compiler has been chosen because generated the best result in simulation with measuring execution time and instructions code generation number than others. We have developed a toolchain to firstly perform Lcode analysis and ILP extraction, and then, to generate VHDL model of corresponding VLIW processor before its testing and validating using the ISE simulator. We have realized some image processing applications on the FPGA Virtex 6 using the proposed approach. We could summarize that the average execution time is improved 2.43 times than the TMS320 C64x processor, and small available hardware resources of the FPGA is used for these implementations