IP-XACT and MARTE based approach for partially reconfigurable systems-on-chip.

International audienceDynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building complex systems remains a daunting task. Recently, approaches based on MDE and UML MARTE standard have emerged which aim to simplify the design of complex SoCs. Moreover, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. In particular, our goal is the creation of the top level description of the system and to exploit IP reuse in order to generate the netlists used by the Xilinx DPR design flow. The methodology is demonstrated by the integration of Deblocking filter IP used in H.264 CODECs into a MicroBlaze based DPR SoC