International audienceIn this paper we present framework for the deployment of hardware IPs at high-levels of abstraction. It is based in a model- driven approach that aims at the automatic generation of Dynamic Partial Reconfiguration designs created in Xilinx Platform Studio (XPS). Contrary to previous approaches, we make use of the IP-XACT standard to facilitate the deployment of hardware IPs, their parameterization and subsequent integration. We propose an extension to the MARTE profile for IP deployment, and we introduce the necessary model transformations to obtain a high- level representation from an IP-XACT component library. These models are then used to create a platform in MARTE that abstracts the technologic aspects of the chose...
Les Systèmes sur puce (soc) sont de plus en plus complexes. Leur conception repose largement sur la ...
On-chip systems (also known as System-on-chip or SoC) are more and more complex. SoC design heavily ...
Effective integration of advanced Systems-on-Chip (SoC) requires extensive reuse of IP modules as we...
International audienceIn this paper we present framework for the deployment of hardware IPs at high-...
International audienceThis paper presents a framework which facilitates the parameterization and int...
International audienceThis paper presents a framework which automates the generation of DPR capable ...
International audienceDynamic Partial Reconfiguration (DPR) has been introduced in recent years as a ...
ISBN: 978-3-9810801-5-5International audienceWe are interested in the problem of improving ipreuse i...
International audienceDynamic Partial Reconfiguration (DPR) has been introduced in recent years as a...
The main contribution of this thesis consists on the proposition and development a Model-driven Engi...
International audienceDynamic Partial Reconfiguration (DPR) has been introduced in recent years as a...
Les Systèmes sur puce (soc) sont de plus en plus complexes. Leur conception repose largement sur la ...
On-chip systems (also known as System-on-chip or SoC) are more and more complex. SoC design heavily ...
Effective integration of advanced Systems-on-Chip (SoC) requires extensive reuse of IP modules as we...
International audienceIn this paper we present framework for the deployment of hardware IPs at high-...
International audienceThis paper presents a framework which facilitates the parameterization and int...
International audienceThis paper presents a framework which automates the generation of DPR capable ...
International audienceDynamic Partial Reconfiguration (DPR) has been introduced in recent years as a ...
ISBN: 978-3-9810801-5-5International audienceWe are interested in the problem of improving ipreuse i...
International audienceDynamic Partial Reconfiguration (DPR) has been introduced in recent years as a...
The main contribution of this thesis consists on the proposition and development a Model-driven Engi...
International audienceDynamic Partial Reconfiguration (DPR) has been introduced in recent years as a...
Les Systèmes sur puce (soc) sont de plus en plus complexes. Leur conception repose largement sur la ...
On-chip systems (also known as System-on-chip or SoC) are more and more complex. SoC design heavily ...
Effective integration of advanced Systems-on-Chip (SoC) requires extensive reuse of IP modules as we...