An efficient FPGA-based architecture for the HEVC intraprediction

National audienceA novel hardware architecture for the High Efficiency Video Coding (HEVC) intra prediction ispresented in this paper, aiming to reduce the computation complexity coming with this moduleand to accelerate the concerned calculations. We propose a new pipelined structure that wenamed Processing Element (PE) to execute all angular modes, and we repeat it in five pathswhich compose our architecture. We propose also another structure perform the Planar mode.This architecture supports all intra prediction modes for all block sizes. The synthesis resultsshow that our solution can run at 213 MHz for FPGA Xilinx Virtex 6 and is capable to processreal time 120 1080p FPS or 30 4K FPS