FPGA Implementations of Piecewise Affine Functions Based on Multi-Resolution Hyperrectangular Partitions

In this paper we propose a digital architecture suited for fast, low-power and small-size electronic implementation of PieceWise Affine (PWA) functions defined over n-dimensional domains partitioned into multi-resolution hyperrectangles. The point location problem, which requires most of the computational effort, is solved through an orthogonal search tree, which is easily and efficiently implementable. In the case of domains partitioned into single-resolution hyperrectangles, a simpler and even faster architecture is proposed. After introducing the new architectures, their key features are discussed and compared to previous architectures implementing PWA functions with domains partitioned into different types of polytopes. Case studies concerning the FPGA implementation of so-called explicit Model Predictive Control (MPC) laws for constrained linear systems are used as benchmarks to compare the different architectures