A High Performance and Low Power Triple-Node-Upset Self-Recoverable Latch Design

The charge sharing effect is becoming increasingly severe due to the continuous reduction of semiconductor process feature size. In the nanoscale digital circuit, the probability of triple-node upset (TNU) is increasing, which seriously affects the reliability of the circuit. To improve the reliability of the digital circuit, this paper presents an optimized TNU self-recoverable latch (HLTNURL). This latch consists of three dual-node-self-recoverable dual interlocked storage cells (DNSR-DICE) and one clock-gating C-element. Whenever any three nodes invert, the latch is able to self-recover to its correct logical values. The HSPICE simulation results indicate that this latch enables full self-recovery of TNU in all cases. In comparison with existing TNU self-recoverable latches, the proposed HLTNURL latch is able to reduce the power dissipation, delay, area overhead, and area-power-delay product (APDP) by 32.41%, 79.73%, 1.32%, and 88% on average. In addition, the HLTNURL latch proposed in this paper has high reliability and low sensitivity to process, voltage, and temperature (i.e., PVT) variations