In this paper we present an integrated circuit implementing piecewise-linear (PWL) functions with three inputs, where each input can be either analog or digital. The PWL function to be implemented can be chosen by properly storing a set of coefficients in a 4 kB external memory. Experimental results are shown that demonstrate the circuit working up to 50 MHz with a maximum power consumption of 3.7 mW. Measurements corresponding to both static and time-varying inputs are provided and discussed
In this paper, we propose an area- and power-efficient reconfigurable architecture for multifunction...
139 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1988.The work presented in this th...
We built as a trial an electronic analog computing elements with linear integrated circuits (IC), wh...
In this paper we present an integrated circuit implementing piecewise-linear (PWL) functions with th...
This paper deals with the circuit implementation of non-linear algebraic bivariate functions. The sy...
Non-linear multiport resistors are the main ingredients in the synthesis of non-linear circuits. Rec...
A methodology is presented for the synthesis of analog circuits using piecewise linear (PWL) approxi...
The paper deals with the design of a universal linear multipart. The circuit is based on digitally c...
The paper deals with the design of a universal linear multipart. The circuit is based on digitally c...
This brief proposes a digital circuit architecture implementing a class of continuous piecewise-affi...
In this paper we review and discuss digital circuit architectures implementing piecewise-affine (PWA...
It is shown how to implement by a mixed-signal circuit a continuous-time dynamical system. The chose...
This paper presents an application specific processor architecture for the calculation of simplicial...
Piecewise Linear (PL) approximation of non-linear behaviour is a well-known technique in synthesis a...
Abstract—This work is concerned with the design automation of analog circuits realizing piecewise li...
In this paper, we propose an area- and power-efficient reconfigurable architecture for multifunction...
139 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1988.The work presented in this th...
We built as a trial an electronic analog computing elements with linear integrated circuits (IC), wh...
In this paper we present an integrated circuit implementing piecewise-linear (PWL) functions with th...
This paper deals with the circuit implementation of non-linear algebraic bivariate functions. The sy...
Non-linear multiport resistors are the main ingredients in the synthesis of non-linear circuits. Rec...
A methodology is presented for the synthesis of analog circuits using piecewise linear (PWL) approxi...
The paper deals with the design of a universal linear multipart. The circuit is based on digitally c...
The paper deals with the design of a universal linear multipart. The circuit is based on digitally c...
This brief proposes a digital circuit architecture implementing a class of continuous piecewise-affi...
In this paper we review and discuss digital circuit architectures implementing piecewise-affine (PWA...
It is shown how to implement by a mixed-signal circuit a continuous-time dynamical system. The chose...
This paper presents an application specific processor architecture for the calculation of simplicial...
Piecewise Linear (PL) approximation of non-linear behaviour is a well-known technique in synthesis a...
Abstract—This work is concerned with the design automation of analog circuits realizing piecewise li...
In this paper, we propose an area- and power-efficient reconfigurable architecture for multifunction...
139 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1988.The work presented in this th...
We built as a trial an electronic analog computing elements with linear integrated circuits (IC), wh...