Symbolic Generation of Constrained Random Logic Cells

A symbolic cell generator (SYC) that can generate the symbolic layout of a generic CMOS logic cell is presented. It accepts as input a SPICE-like netlist describing circuit components, connectivity, and the list of the I/O pins. Using this generator, the user can specify topological constraints on pin and transistor positions, the maximum lengths of polysilicon and diffusion wires, and a preferred layer for each electrical node. Cells are generated according to optimization criteria that take into account not only geometric factors, such as cell area, aspect ratio, and wirelength, but also electrical features, namely capacitance to the substrate and contact and via minimization. The generator's placement strategy includes transistor clustering into regions, global region placement by linear ordering, and two-dimensional local transistor placement. The routing combines Steiner trees and Lee algorithms. Object-oriented programming paradigms were used in the implementation of the program, written in C++ language. Experimental results for small and medium-sized cells are presented