This paper describes a three-layer maze router for chip-planning applications. The router contains a general and flexible algorithm to wire connections. It is also shown how this algorithm can effectively help to choose better heuristics in order to solve routing problems
This paper introduces a new, practical routing algorithm, Maze-routing, to tolerate faults in net...
Thesis: S.M., Massachusetts Institute of Technology, Sloan School of Management, Operations Research...
Chameleon, a channel router for three layers of interconnect, has been implemented to accept specifi...
In this thesis, we explore various parallel processing methods for concurrent multi-layer VLSI routi...
A channel router is an important design aid in the design automation of VLSI circuit layout. Many al...
This paper describes the implementation of the L3 maze routing accelerator in an FPGA. L3 supports ...
The routing problem of VLSI layout design is computationally very expensive because of the inherent ...
This paper describes the design and implementation of an FPGA-based multilayer maze routing accelera...
This paper describes a new detailed routing algorithm that has been designed specifically for the ty...
[[abstract]]A general-purpose routing algorithm is proposed. Ideas behind both the maze-running algo...
Recently, to the extent allowed by the fabricating technology, approaches have been made to develop ...
The routing of nets or a set of interconnection points is a complete intensive application encounter...
This report describes the problem of printed circuit board routing. An overview of circuit board con...
Parameterised configurations for FPGAs are configuration bitstreams of which some of the bits are de...
A new multilayer, general-area, multichip module (MCM) routing algorithm, called MCG, is introduced....
This paper introduces a new, practical routing algorithm, Maze-routing, to tolerate faults in net...
Thesis: S.M., Massachusetts Institute of Technology, Sloan School of Management, Operations Research...
Chameleon, a channel router for three layers of interconnect, has been implemented to accept specifi...
In this thesis, we explore various parallel processing methods for concurrent multi-layer VLSI routi...
A channel router is an important design aid in the design automation of VLSI circuit layout. Many al...
This paper describes the implementation of the L3 maze routing accelerator in an FPGA. L3 supports ...
The routing problem of VLSI layout design is computationally very expensive because of the inherent ...
This paper describes the design and implementation of an FPGA-based multilayer maze routing accelera...
This paper describes a new detailed routing algorithm that has been designed specifically for the ty...
[[abstract]]A general-purpose routing algorithm is proposed. Ideas behind both the maze-running algo...
Recently, to the extent allowed by the fabricating technology, approaches have been made to develop ...
The routing of nets or a set of interconnection points is a complete intensive application encounter...
This report describes the problem of printed circuit board routing. An overview of circuit board con...
Parameterised configurations for FPGAs are configuration bitstreams of which some of the bits are de...
A new multilayer, general-area, multichip module (MCM) routing algorithm, called MCG, is introduced....
This paper introduces a new, practical routing algorithm, Maze-routing, to tolerate faults in net...
Thesis: S.M., Massachusetts Institute of Technology, Sloan School of Management, Operations Research...
Chameleon, a channel router for three layers of interconnect, has been implemented to accept specifi...