Add to ORKGThe efficiency of a symbolic compactor is closely related to the quality of the physical layout produced. In particular, a reduction of the dimensions of the chip can be achieved by eliminating useless components, optimizing wires, and performing a proper rearrangement of the components positions. In this paper, some optimization strategies are described which make it possible to achieve significant lrnprovements in the physical layout produced by a symbolic compactor
With the increasing complexity of modern VLSI circuits, achieving high quality built-in self-test r...
Abstract. We propose a new approach to tackling multi-objective optimization problems. Our method us...
: The paper deals with a problem encountered in the physical implementation of circuits on the PCB a...
This paper describes a new approach for IC layout and compaction. The compaction problem is translat...
This paper presents a survey and a taxonomy of layout compaction algorithms, which are an essential ...
Thesis (Ph. D.)--University of Rochester. Dept. of Computer Science, 1984. Simultaneously published ...
A compacter takes as input a VLSI layout and produces as output an equivalent layout of smaller area...
A compacter takes as input a VLSI layout and produces as output an equivalent layout of smaller are...
This technical report is prepared to record the preliminary work carried out in beginning a research...
Partial reconfiguration allows parts of the reconfigurable chip area to be configured without affect...
The problem of compacting a set of test sequences for sequential circuits is modeled here with the h...
Symbolic design optimization: a computer aided method to increase monotonicity through variable refo...
In this paper we study the two-dimensional compaction of integrated circuit layouts. A curvilinear r...
In general, the shrinkage of the powder compact during the sintering process is not uniform due to t...
A new method of compaction for VLSI circuits is presented. Compaction is done simultaneously in two ...
With the increasing complexity of modern VLSI circuits, achieving high quality built-in self-test r...
Abstract. We propose a new approach to tackling multi-objective optimization problems. Our method us...
: The paper deals with a problem encountered in the physical implementation of circuits on the PCB a...
This paper describes a new approach for IC layout and compaction. The compaction problem is translat...
This paper presents a survey and a taxonomy of layout compaction algorithms, which are an essential ...
Thesis (Ph. D.)--University of Rochester. Dept. of Computer Science, 1984. Simultaneously published ...
A compacter takes as input a VLSI layout and produces as output an equivalent layout of smaller area...
A compacter takes as input a VLSI layout and produces as output an equivalent layout of smaller are...
This technical report is prepared to record the preliminary work carried out in beginning a research...
Partial reconfiguration allows parts of the reconfigurable chip area to be configured without affect...
The problem of compacting a set of test sequences for sequential circuits is modeled here with the h...
Symbolic design optimization: a computer aided method to increase monotonicity through variable refo...
In this paper we study the two-dimensional compaction of integrated circuit layouts. A curvilinear r...
In general, the shrinkage of the powder compact during the sintering process is not uniform due to t...
A new method of compaction for VLSI circuits is presented. Compaction is done simultaneously in two ...
With the increasing complexity of modern VLSI circuits, achieving high quality built-in self-test r...
Abstract. We propose a new approach to tackling multi-objective optimization problems. Our method us...
: The paper deals with a problem encountered in the physical implementation of circuits on the PCB a...