Statistical Investigation of Anomalous Fast Erase Dynamics in Charge Trapping NAND Flash

In NAND Flash non-volatile memories the erase operation drives the memory cells threshold voltage toward negative values, barely representing a concern for Multi-Level architectures. However, during the analysis of the erase dynamics in Charge Trapping (CT) memory arrays using an Incremental Step Pulse Erase algorithm, it has been found that a small population of memory cells ( 2%) may randomly exhibit anomalous fast erase dynamics which causes threshold voltage fluctuations during cycling operations. The purpose of this letter is to provide a statistical characterization of this phenomenon in CT-NAND Flash arrays, thus helping the comprehension of its underlying physical mechanisms