This paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip network (NoC) for bisynchronous communication channels. Concurrent BIST operations are carried out after reset at each switch, thus resulting in scalable test application time with network size. The key principle consists of exploiting the inherent structural redundancy of the NoC architecture in a cooperative way for the effective diagnosis and error detection. At-speed testing of stuck-at faults can be performed in less than 4000 cycles regardless of their size, with an hardware overhead of less than 30%
(ICT-215881) supported by the European Commission. Integrated circuits (IC) targeting at the streami...
Most multi- and many-core integrated systems are currently designed by following a globally asynchro...
Special Issue: 99International audienceThis paper addresses the important issue of fault tolerance i...
This paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip network ...
In this paper, we present a novel built-in self-test methodology for testing the inter-switch links ...
This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if th...
This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if th...
In some application domains (e.g., mission-critical systems), proactive detection of reliability thr...
In some application domains (e.g., mission-critical systems), proactive detection of reliability thr...
Safety-critical systems embedding concurrent on-line testing techniques are vulnerable to design iss...
The demands of future computing, as well as the challenges of nanometer-era VLSI design, will requir...
© ACM, 2013. This is the author's version of the work. It is posted here by permission of ACM for yo...
Most built-in self-test architectures use pseudo-random test pattern generators. However, whenever t...
Most BIST architectures use pseudo-random test pattern generators. However, whenever this technique ...
This paper presents an offline/online concurrent scan based built-in-self-test (scan-BIST) method fo...
(ICT-215881) supported by the European Commission. Integrated circuits (IC) targeting at the streami...
Most multi- and many-core integrated systems are currently designed by following a globally asynchro...
Special Issue: 99International audienceThis paper addresses the important issue of fault tolerance i...
This paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip network ...
In this paper, we present a novel built-in self-test methodology for testing the inter-switch links ...
This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if th...
This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if th...
In some application domains (e.g., mission-critical systems), proactive detection of reliability thr...
In some application domains (e.g., mission-critical systems), proactive detection of reliability thr...
Safety-critical systems embedding concurrent on-line testing techniques are vulnerable to design iss...
The demands of future computing, as well as the challenges of nanometer-era VLSI design, will requir...
© ACM, 2013. This is the author's version of the work. It is posted here by permission of ACM for yo...
Most built-in self-test architectures use pseudo-random test pattern generators. However, whenever t...
Most BIST architectures use pseudo-random test pattern generators. However, whenever this technique ...
This paper presents an offline/online concurrent scan based built-in-self-test (scan-BIST) method fo...
(ICT-215881) supported by the European Commission. Integrated circuits (IC) targeting at the streami...
Most multi- and many-core integrated systems are currently designed by following a globally asynchro...
Special Issue: 99International audienceThis paper addresses the important issue of fault tolerance i...