Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors

There is still a significant gap between the optical network-on-chip (NoC) concept and a mature interconnect technology with practical relevance. Current research aims at bridging this gap by evolving basic optical components and by developing ad-hoc design tools to enable their use for system-level design. This paper points out another cause for the design predictability gap of optical NoC topologies, namely the physical placement of network interfaces in the target floorplan. Building on this awareness, the paper compares power efficiency of the most relevant topologies proposed so far for wavelength-routed optical NoCs in the context of a 3D-stacked multi-core processor