A statistical model of Erratic Erase based on an automated Random Telegraph Signal characterization technique

We propose a new statistical model of the erratic erase based on a new RTS analysis technique. The experimental analysis revealed new interesting features of the erratic erase phenomenon. The overall erased threshold voltage distribution, including tail bits, can be modeled by taking into account the erratic erase behavior whose characteristics can easily be measured by common cycling experiments. The statistical model of the erased threshold voltage obtained in this way can then be used to perform statistical simulation of the bitline leakage current, thus providing a powerful tool in memory design and optimization