Networks on Chips: A Synthesis Perspective

To face increasing requirements for computational density in embedded chips, MultiProcessor Systems-on-Chip (MPSoCs) are being widely deployed. This evolution increases communication requirements, therefore new, more scalable, on-chip interconnect fabrics are being called for. Networkson- Chip (NoCs) appear to solve the upcoming scalability issue. However, it is presently unclear how exactly NoCs can position themselves in terms of performance/area tradeoff. Since NoCs are supposed to span across the whole chip area, difficult questions associated to chip layout arise. Specifically, the delay impact of long-range wiring resources is unknown, and the delay estimation provided by synthesis tools must be verified against post-placement figures. This paper will address such question marks, by showing a complete NoC synthesis flow going down to the layout level. The experimental results include assessment of a complete placed NoC instance and analysis of single switches when synthesized in varying configurations