Spice-Accurate SystemC Macromodels of Noisy On-Chip Communication Channels

With the advent of nanoscale technologies, even RTL and system designers must consider interconnect analysis to provide predictable performance, reliability and meet power budgets. However, system-wide modeling of high-speed interconnects using conventional circuit simulators such as SPICE can become prohibitively CPU expensive. We propose to formulate interconnectmacromodels analytically in terms of arbitrary noise source assumptions and to integrate them into the SystemC communication abstractions. SPICE-accuracy within 5% is proved on average for HDL simulations, and a few case studies illustrate the applicability of the developed modelling and simulation framework for fast exploration of physical channel configuration and performance estimation