44.6% processing cycles reduction in GSM voice coding by low-power reconfigurable co-processor architecture

Atzori E
CARTA, SALVATORE MARIO
RAFFO, LUIGI

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Publication date

January 2002

DOI

10.1049/el:20021019

ISSN

0013-5194

Citation count (estimate)

Abstract

A reconfigurable architecture oriented to low-power digital signal processing is presented, synthesised and tested on ETSI-GSM voice coding algorithms. An overall reduction of 44.6% cycles with respect to standard RISC processors is obtained. Such improvement together with locality and temporal correlation allows a reduction of power consumption

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44.6% processing cycles reduction in GSM voice coding by low-power reconfigurable co-processor architecture

Abstract

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44.6% processing cycles reduction in GSM voice coding by low-power reconfigurable co-processor architecture

Abstract

Extracted data

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