DELAY INSENSITIVE MICRO-PIPELINED COMBINATIONAL LOGIC

Considerable efforts are being done in developing synthesis systems for hybrid asynchronous circuits, that is involving delay insensitive (DI) and non-DI parts. This paper presents a micro-architecture design methodology the gets that benefits of a DI control-path and a self-timed data-path. The control-path is automatically synthesized as a purely DI circuit from a behavioral specification. The data-path is partially designed by using locally clocked functional blocks, for registers and multiplexers, and partially by using DI combinational units. In particular, we focus on pipeline combinational units, composed of dedicated standard cells implementing Boolean functions in the double-rail convention. Each cell has a storage element, governed by request/acknowledge signals, allowing us to realize a DI micropipeline in which a stage is a single logic gate. No hardwired delays are needed. The approach is well suited for automated design using extant synthesis and optimization tools for combinational logic. A first example of utilization is reported, to evaluate performance and cost