A novel CMOS logic style with data independent power consumption

We propose a novel dynamic CMOS logic style to protect security devices against power attacks. The logic is based on signals with 3 possible states and operates with a power consumption ideally independent of both the logic values and the sequence of data. We have designed a set of logic gates and a flip-flop and compared those to Static Complementary CMOS implementations in terms of correlation between data and power consumption, speed, area, and total power dissipation