Design of a digital multi-precision multiply-accumulate unit

Machine Learning requires an enormous amount of mathematical computation per second. Several architectures have been proposed to match the computation requirements and improve the calculation efficiency. Among these, the Systolic Array accelerators show promising results. These accelerators are composed of several Processing Elements (PEs), arranged on multiple symmetrical lines, which include a Multiply-And-Accumulate module. Specific multi-precision multipliers are increasingly popular since they can execute different precision multiplications and they can be integrated into Systolic Array accelerators. In this work, a multi-precision multiplier is proposed. The objective of the design is to build up a multiplier formed by combining smaller and equal multipliers. Depending on the number of small multipliers that are used, the size of the final multiplier changes. The mathematical foundation is based on decomposing the operands as the addition of several numbers and then applying the distributive and associative properties of mathematics. Different designs have been implemented with small multipliers able to execute 4x4 and 8x8 multiplications. A total of six multipliers have been implemented: three multipliers are made with 4x4 small multipliers and their output size is 16,32,64. The other three multipliers are realized with 8x8 small multipliers and their output size is 32,64,128. The multiplier benefits of hardware re-utilization and shows promising results in terms of area and power consumption. Less energy is consumed and less surface area is required compared to previously developed solutions. Compared to other structures performing similar functions, reusing multipliers can save about 30% of the area with a penalty of only 8% of the delay