DESIGN AND ANALYSIS OF CASCADED MULTILEVEL INVERTER TOPOLOGY

Inverter is an important tool to convert DC circuit to AC circuit. It is very widely used in the industry especially in powering up motors. The conventional H-bridge multilevel inverter requires high number of voltage sources to operate. In this thesis, an improved cascaded H-bridge multilevel inverter is proposed. The conventional H- bridge multilevel inverter is modified by using ternary number system on ratio-based voltage sources to produce multilevel inverter to reduce the number of voltage sources. Its advantages are reduced switching components, reduced voltage sources, reduced size, reduced cost and easier to implement. The limitations are the demand for higher speed and power of microprocessor and the necessity to regulation of voltage sources at certain values. The topologies and control techniques of multilevel inverters are studied. minimizing the switching components, the voltage sources to reduce the cost and complexity. Several topologies are discussed in this thesis and a comparison between the proposed topology is compared with the conventional cascaded H-bridge multilevel inverter topology. Simulations are performed to analyse and compare the performance between three multilevel inverter topologies of a 7, 9, 11 level multilevel inverter. The analyses on the performance of the three topologies are based on the fundamental voltage, output voltage waveform, output current waveform and total harmonic distortion (THD) from both the simulation and experimental setup results