VCO DEVELOPMENT USING 130nm CMOS TECHNOLOGY

This dissertation focuses on the simulation of a VCO that is optimized for its phase noise properties by utilizing Cadence tools. Besides, a detailed study on the main causes of phase noise in a VCO and techniques of improving the VCO’s phase noise was also conducted in the midst of VCO design. A top-down approach was employed for the design process whereas a bottom-up approached was employed for verification purposes to ensure robustness of the design using Silterra 130nm CMOS process technology. As a result, a fully CMOS based VCO operating at 5GHz centre frequency was designed using a PMOS based varactor for tuning purposes. Overall, the VCO has been reported to have a nominal phase noise of -133.38 dBc/Hz at 10 MHz with 10% tuning range using 1.2V supply voltage and 5.23 mA current. During power down mode, the VCO has leakage current of 3.598pA. The VCO was tested across supply voltage and temperature variations for its robustness