Verification Approach Using Uvm

Verification is one of the most important activity in the flow of ASIC/VLSI design. Verification consumes large amount of design flow cycle & efforts to ensure design is bug free. Hence it becomes intense requirement for powerful and reusable methodology for verification. The Universal Verification Methodology (UVM) is a powerful verification methodology that was architected to be able to verify a wide range of design sizes and design types. UVM is derived from other methodology like VMM, OVM, eRM. It is useful to verify designs in any language like verilog, VHDL, System Verilog. Reusable verification environment is possible using UVM & hence saving considerable time in Verification cycle. This paper talks about the architecture of environment using UVM. It also focuses on terms & ways used in Verification using UVM