A distortion model for pipeline analog-to-digital converters

Pipeline analog-to-digital converters (ADC) are widely used to achieve high resolution and moderately high sampling frequency. In typical implementations, linearity is often limited by capacitor mismatch and finite amplifier gain. The impact of these non ideal effects on the overall linearity of the ADC has been addressed in this paper, obtaining a model to estimate total harmonic distortion (THD), given capacitors' sizing and amplifiers' gain. This model enables the designer to analyze the impact of error sources in each stage separately, and to perform Monte Carlo simulations. In this way, design rules can be obtained to properly size each multiplying digital-to-analog converter (MDAC) in the first stages of the design process