This paper introduces a new, practical routing algorithm, Maze-routing, to tolerate faults in network-on-chips. The algorithm is the first to provide all of the following properties at the same time: 1) fully-distributed with no centralized component, 2) guaranteed delivery (it guarantees to deliver packets when a path exists between nodes, or otherwise indicate that destination is unreachable, while being deadlock and livelock free), 3) low area cost, 4) low reconfiguration overhead upon a fault. To achieve all these properties, we propose Maze-routing, a new variant of face routing in on-chip networks and make use of deflections in routing. Our evaluations show that Maze-routing has 16X less area overhead than other algorithms that pro...
A fault-tolerant adaptive wormhole routing function for Networks-on-Chips (NoCs) is presented. The n...
International audienceParallelized kernels for operations research belong to the class of the diffus...
The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as ...
This paper introduces a new, practical routing algorithm, Maze-routing, to tolerate faults in networ...
International audienceNoCs (Networks-on-Chip) are an attractive alternative to communication buses f...
International audienceNetworks-on-Chips (NoCs) are considered to be the paradigm of choice for on-ch...
Abstract—Fault-tolerant routing is the ability to survive failure of individual components and usual...
Downscaled complementary metal-oxide semiconductor (CMOS) technology feature sizes have enabled mass...
Due to the faults in system fabrication and run time, designing an efficient fault-tolerant routing ...
In 2D mesh Network on Chips (NoCs), fault-tolerant algorithms usually deactivate healthy nodes to fo...
This paper proposes a look-ahead, fault-tolerant and congestion-aware routing algorithm for Networks...
There is a seemingly endless miniaturization of electronic components, which has enabled designers t...
A fault-tolerant routing algorithm in Network-on-Chip (NoC) architectures provides adaptivity for on...
We develop a routing algorithm for fault tolerant 2-D mesh Network-on-Chips (NoCs) with permanent fa...
As silicon features approach the atomic scale, the Networks-on-Chip (NoCs) are becoming more suscept...
A fault-tolerant adaptive wormhole routing function for Networks-on-Chips (NoCs) is presented. The n...
International audienceParallelized kernels for operations research belong to the class of the diffus...
The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as ...
This paper introduces a new, practical routing algorithm, Maze-routing, to tolerate faults in networ...
International audienceNoCs (Networks-on-Chip) are an attractive alternative to communication buses f...
International audienceNetworks-on-Chips (NoCs) are considered to be the paradigm of choice for on-ch...
Abstract—Fault-tolerant routing is the ability to survive failure of individual components and usual...
Downscaled complementary metal-oxide semiconductor (CMOS) technology feature sizes have enabled mass...
Due to the faults in system fabrication and run time, designing an efficient fault-tolerant routing ...
In 2D mesh Network on Chips (NoCs), fault-tolerant algorithms usually deactivate healthy nodes to fo...
This paper proposes a look-ahead, fault-tolerant and congestion-aware routing algorithm for Networks...
There is a seemingly endless miniaturization of electronic components, which has enabled designers t...
A fault-tolerant routing algorithm in Network-on-Chip (NoC) architectures provides adaptivity for on...
We develop a routing algorithm for fault tolerant 2-D mesh Network-on-Chips (NoCs) with permanent fa...
As silicon features approach the atomic scale, the Networks-on-Chip (NoCs) are becoming more suscept...
A fault-tolerant adaptive wormhole routing function for Networks-on-Chips (NoCs) is presented. The n...
International audienceParallelized kernels for operations research belong to the class of the diffus...
The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as ...