2005 International Symposium on System-on-Chip: Proceedings

this paper presents two asynchronous links between any two independently clocked synchronous modules. The first link is based on using synchronizers and synchronous and asynchronous FIFOs which compensates the increase of latency due to synchronization. Due to this the latency of this link is reduced to 2.08nsee. The mean time between failures of this link is 35 years, which is more than enough for any design. The second link generates clock for each module locally and stops it whenever there is communication between module and link. In this link there is no synchronization failure at all. The latency and power consumption of both links are very small which makes them efficient links for SoC. Since the two link architectures let the use of different clocks in each synchronous module, it makes the system modular and enables easy reusage of different synchronous modules in the system. The circuits are simulated using the analog environment of Spectre with 0.13um technology