Dielectric influence on IV curve of graphene field effect transistor

In this article, we have studied the influence of Si3N4 and SiO2 thin film gate dielectrics on the current-voltage characteristics of the graphene-based transistor. The test structure of graphene transistor was fabricated with the top and back gate. Graphene has been produced by chemical vapor deposition, and then transferred to the silicon dioxide on a silicon wafer. The channel of the transistor has been formed by etching in oxygen plasma through a photolithographic mask. Metals electrodes of the drain, source, and gate were deposited by resistive evaporation in a vacuum. It was used titanium / aluminum with a thickness of 50/200 nm. In the case of the back gate, silicon dioxide was used, obtained by thermal oxidation of the silicon substrate. For top gate was used silicon nitride deposited by plasma chemical deposition. It was demonstrated that field effect is more pronounced for the case of SiO2 back gate compare to the Si3N4 top gate. For the SiO2 back gate we have observed that the source- drain current decreases, from 2 mA to 3 mA, with increasing the gate voltage, from 0 to 40 V, at constant source-drain voltage, 2 V. In case of Si3N4 top gate the modulation of source-drain current was not significant for the comparable electric field strength. Based on the value of gate voltage for current minima in transfer function the poor quality of Si3N4 -graphene interface is concluded. © 2016 SPIE.