HPCG for FPGAs: A Data-Centric Approach

Field programmable gate arrays (FPGAs) have become increasingly popular in the high-performance computing (HPC) community due to their versatility in providing application-specific hardware acceleration. The main advantage of an FPGA is that it can be reconfigured as needed for each application. This property places the FPGA between general-purpose hardware like CPUs and custom-built ASICs. With the introduction of HBM memory into modern FPGAs and the ability to reduce data movement significantly, FPGAs have become very effective at tackling memory-bound HPC workloads. One of the most popular metrics used to evaluate the performance of supercomputing systems on memory-bound applications is the High-Performance Conjugate Gradient (HPCG) benchmark. The DaCe framework provides an abstraction that allows for programming in the context of FPGAs, GPUs, and CPUs. This thesis will discuss our efforts in creating an HPCG implementation that targets the FPGA architecture using the DaCe Python API. We discuss the design choices we made for our HPCG DaCe Python implementation, which includes how we handled the restrictions imposed by using Python with the DaCe framework and the FPGA-optimized kernel implementations. In the final chapter, we address possible performance improvements regarding our implementation and the DaCe framework