Video framebuffers are usually used in video processing systems to store an entire frame of video data required for processing. These framebuffers make extensive use of random access memory (RAM) technologies and interfaces that use them. Recent trends in the high-speed video discuss the use of higher speed memory interfaces such as DDR4 (double-datarate 4) and HBM (high-bandwidth memory) interfaces. To meet the demand for higher image resolutions and frame rates, larger and faster framebuffer memories are required. While it is not feasible for software to read and process parts of an image quickly and efficiently enough due to the high speed of the incoming video, a hardware-based video processing solution poses no such limitation. Existin...
Abstract—In this paper, we present a cache scheme targeting hardware implementation to reduce the ba...
Implementing a real-time image-processing algorithm on a serial processor is difficult to achieve b...
This paper presents a VLSI architecture for a low complexity motion estimation algorithm, referred t...
Video processing usually requires one to read in an entire image into a framebuffer, usually taking ...
The architecture of the present video processing units in consumer systems is usually based on vario...
In this dissertation we present methodologies and evaluations aiming at increasing the efficiency of...
The main challenge for reducing the design effort cost of complex systems on chip is to pursue more ...
Abstract—The frame memory has long been the dominant component in a video decoder in terms of energy...
Performance requirements for video decoding will continue to rise in the future due to the adoption ...
The thesis, entitled PC-BASED VIDEO FRAME GRABBER aims to capture one frame of a video image, and th...
Abstract—This paper proposes a combined frame memory architecture which is smaller in size and is po...
An important question is whether emerging and future applications exhibit sufficient parallelism, in...
The microprocessor industry trend towards many-core architectures introduced the necessity of devisi...
An important question is whether emerging and future applications exhibit sufficient parallelism, in...
Efficient and dedicated hardware architecture and accelerator micro-engines are crucial implementati...
Abstract—In this paper, we present a cache scheme targeting hardware implementation to reduce the ba...
Implementing a real-time image-processing algorithm on a serial processor is difficult to achieve b...
This paper presents a VLSI architecture for a low complexity motion estimation algorithm, referred t...
Video processing usually requires one to read in an entire image into a framebuffer, usually taking ...
The architecture of the present video processing units in consumer systems is usually based on vario...
In this dissertation we present methodologies and evaluations aiming at increasing the efficiency of...
The main challenge for reducing the design effort cost of complex systems on chip is to pursue more ...
Abstract—The frame memory has long been the dominant component in a video decoder in terms of energy...
Performance requirements for video decoding will continue to rise in the future due to the adoption ...
The thesis, entitled PC-BASED VIDEO FRAME GRABBER aims to capture one frame of a video image, and th...
Abstract—This paper proposes a combined frame memory architecture which is smaller in size and is po...
An important question is whether emerging and future applications exhibit sufficient parallelism, in...
The microprocessor industry trend towards many-core architectures introduced the necessity of devisi...
An important question is whether emerging and future applications exhibit sufficient parallelism, in...
Efficient and dedicated hardware architecture and accelerator micro-engines are crucial implementati...
Abstract—In this paper, we present a cache scheme targeting hardware implementation to reduce the ba...
Implementing a real-time image-processing algorithm on a serial processor is difficult to achieve b...
This paper presents a VLSI architecture for a low complexity motion estimation algorithm, referred t...